1. Field of the Invention
The present invention relates to the field of integrated circuit design and more particularly to latchup of a CMOS circuit.
2. Background Information
Conventional CMOS (Complimentary Metal Oxide Semiconductor) technologies cannot permanently store information. During normal operation and normal biasing of a CMOS integrated circuit (IC), a general user cannot permanently store information because the CMOS circuitry cannot be physically altered in any lasting way. No matter how a CMOS IC is utilized by a general user, information stored and manipulated by the IC is entirely erased upon interruption of its power supply. In contrast, memory technologies such as Erasable Programmable Read Only Memory (EPROM) are capable of permanently storing information even in the absence of a power supply due to their ability to physically alter the location of charged particles. CMOS technology, being faster than EPROM technology, is typically used to manufacture microprocessors which are used to execute mathematical computations in a computer. EPROM technology is typically used to manufacture memory chips which store the information in a computer when the computer is turned off.
While it would be desirable for CMOS ICs to incorporate permanent memory storage capabilities, prior attempts to combine CMOS with EPROM technologies have proven to be uneconomical. However, CMOS IC designers have devised limited methods for permanently altering the physical structure of post-fabricated CMOS circuits, thereby allowing such circuits to store a small amount of information. One such method involves designing fuses into an IC and selectively blowing these fuses during operation of the IC such that the short circuits resulting from unblown fuses and open circuits resulting from blown fuses may be interpreted by the IC as permanently stored information. Unfortunately, this method of blowing fuses in an IC has heretofore had significant limitations.
FIG. 1 illustrates an IC fuse along with its schematic representation. To create a fuse in an IC, a designer must first determine the desired location of the fuse along a conductive path in the IC. As illustrated in FIG. 1, the fuse has been placed in region 12 along conductive path 10. Width 14 of interconnect line 10 outside of the narrow region 12 is approximately three to four times the width 13 within the narrow region 12. Electrons traveling through metal interconnect line 10 are forced through the narrow region 12 at a higher density than the density at which these electrons travel through the wider regions of the interconnect. Because the electrons traveling through narrow region 12 travel at a higher density, region 12 of metal interconnect line 10 is more susceptible to the effects of electromigration than are the wider regions of metal interconnect line 10.
Electromigration is a phenomenon by which conductive material is pushed down the path of electron travel by the electrons moving through the conductive material. The higher the electron density, the stronger the migration force. As a result of electromigration of the conductive material within region 12, an open circuit will result if the current is high enough. In addition, narrow region 12 represents a higher resistance to the flow of current than does the wider region of metal interconnect line 10. As a result of this increased resistance, a high current flowing through metal interconnect line 10 can cause the conductive material within region 12 to heat up and ultimately melt away. This is another way in which an open circuit may be created within region 12 of metal interconnect line 10.
Therefore, important factors to consider in creating an open circuit are the amount of current flowing through metal interconnect line 10, the cross-sectional area as seen by such a current within region 12, and the temperature of interconnect line 10. The cross-sectional area seen by a current flowing through metal interconnect line 10 within region 12 is the product of the width 13 of region 12 times the thickness (depth into the page) of metal interconnect line 10. For conventional CMOS process technology, the width 13 may be approximately 1 micron while the thickness of metal interconnect line 10 may be approximately 3,000 .ANG.. Assuming metal interconnect line 10 is aluminum, a current in excess of approximately 10 mA should be enough to cause an open circuit in metal interconnect line 10 within the region 12 at normal operating temperatures. Of course, increasing or decreasing the width 13 or the thickness of metal interconnect line 10 will proportionately increase or decrease, respectively, the current required to cause an open circuit within region 12. For example, approximately 20 mA would be required to cause an open circuit if the width 13 were doubled from 1 to 2 microns, and approximately 30 mA would be required if the width 13 were increase to 3 microns, etc.
Narrow region 12 of metal interconnect line 10 is a fuse. Forcing a current through region 12 which is high enough to cause an open circuit is called "blowing" the fuse. Fuse 12 in metal interconnect line 10 is represented schematically in diagram 17 by the fuse 15. Fuse 15 represents a conductive region of interconnect line 11 which is susceptible to blowing open upon subjecting interconnect line 11 to high currents.
A significant limitation of the fuse of FIG. 1 is the requirement that the metal interconnect line outside of the fuse region be wide enough to handle the large current required to blow the fuse. To be sure that the metal interconnect line outside of the fuse region is not adversely affected by such high currents, it is not uncommon for the width of these interconnect lines to be in excess of 10 microns. Similarly, transistors coupled to interconnect lines containing fuses also need to be very large in order to handle the high currents necessary to blow the fuses. This limitation severely limits the applicability of fuse blowing techniques for use in conventional CMOS circuits as described below.
FIG. 2 illustrates a circuit comprising a fuse 22 used to selectively disable contact pad 20. Contact pads 20 and 21 exist in the peripheral region of the integrated circuit device to which they are coupled. Contact pad 20 is coupled to node 27 through fuse 22. Node 27 is coupled to the drain of N channel transistor 25 through line 24. Node 27 is also coupled to the remainder of the IC device through interconnect line 23. The source of transistor 25 is tied to V.sub.SS while its gate is coupled to pad 21. During normal operation of the IC device, pad 21 is grounded in order to turn off transistor 25. With fuse 22 intact, electronic signals coupled to input pad 20 are transmitted through fuse 22 and through interconnect line 23 to the remainder of the integrated circuit device.
Suppose, however, that it becomes desirable to disengage pad 20 from the internal operations of the IC device. This can be accomplished by blowing fuse 22. In order to blow fuse 22, the voltage at pad 21, which is coupled to the gate of transistor 25, must be raised thereby turning on transistor 25. By turning on transistor 25, a conductive path between pad 20 and V.sub.SS will be established. Then, by applying high voltage to pad 20, a large current may be forced through fuse 22, blowing it open. In this manner, pad 22 may be effectively disengaged from the IC device.
As can be seen in FIG. 2, in order to blow fuse 22, it is necessary to drive a large current through the path comprising pad 20, fuse 22, node 27, interconnect line 24, transistor 25, and interconnect line 26 to V.sub.SS. If fuse 22 is not the weakest link in this path from pad 20 to V.sub.SS, it will not be possible to disengage pad 20. For example, if interconnect line 24 is too narrow, line 24 may blow open instead of fuse 22 upon turning on transistor 25. If this happens, the high current path will be broken between node 27 and transistor 25 before fuse 22 is blown, cutting off the high current flow through fuse 22. As a result, pad 20 will continue to be coupled to the IC device through fuse 22 and interconnect line 23. Also, note that the dimensions of transistor 25 must be large enough to reliably handle the current required to blow fuse 22. For example, if transistor 25 is too small, the source/drain resistance of the transistor will be too high, and the current through fuse 22 will be severely limited by this resistance, possibly preventing fuse 22 from blowing.
Therefore, it is necessary that interconnect lines 24, 26, and transistor 25 be large enough to reliably handle the high current required to blow fuse 22. However, by designing interconnect lines 24, 26, and transistor 25 using large dimensions, valuable area on the semiconductor substrate is used up. This reduces the packing density of the overall IC device, increasing manufacturing costs. One partial solution to this problem may be to reduce the size of transistor 25, then compensate for the increased source/drain resistance by increasing the voltage at pad 20 to drive a larger current through fuse 22. However, this would require a dual voltage supply and may only be accomplished by the IC manufacturer during testing of the IC device. As a result, circuits of the type depicted in FIG. 2 must be placed in the inactive, peripheral region of an IC device. Circuits having such wide interconnect lines and large transistor dimensions cannot be placed within the dense, active region in the interior of an IC device because the value of semiconductor "real estate" is at a premium in this active, interior region. Generally, only minimum dimension transistors and interconnect lines may be economically fabricated in the interior region of an IC device.
FIG. 3 illustrates a PROM (Programmable Read Only Memory) IC device utilizing fuses as a means for programming. Each cell in the PROM of FIG. 3 is substantially identical to its adjacent cell. Analyzing one of these cells, cell 36, it can be seen that it comprises transistor 32 whose gate is coupled through interconnect line 34 to word line 30. The drain of transistor 32 is coupled through interconnect line 37 to supply voltage V.sub.DD while the source of transistor 32 is coupled through fuse 33 and interconnect line 35 to bit line 31. To program cell 36 of the PROM of FIG. 3, fuse 33 is either blown or left intact. If blown, applying a high voltage to word line 30 will turn on n-channel transistor 32, but supply voltage V.sub.DD will not be transmitted to bit line 31 because the source of transistor 32 will be electrically isolated from bit line 31 due to the blown fuse 33. Therefore, if fuse 33 is blown, and word line 30 is selected, bit line 31 will carry a low voltage (assuming bit line 31 is biased to a low voltage) indicating a logical "0" at this bit position. If, on the other hand, fuse 33 is left intact and a high voltage is applied to word line 30, n-channel transistor 32 will turn on and pull bit line 31 up to V.sub.DD. Therefore, when word line 30 is selected, and fuse 33 is intact, bit line 31 will be raised to a high voltage representing a logical "1" at this bit position.
In order to properly blow fuse 33, it is necessary for the interconnect lines and transistors in the high current loop between the supply voltage V.sub.DD and the ground plane V.sub.SS to be large enough to handle the current necessary to blow fuse 33. In cell 36, the high current loop used to blow fuse 33 consists of interconnect line 37 coupled to V.sub.DD, n-channel transistor 32, fuse 33, interconnect line 35, and bit line 31 which is coupled to V.sub.SS. Clearly, as the PROM array illustrated in FIG. 3 grows in size and complexity, it becomes impractical to use the required large dimensions for the interconnect lines and transistors in the high current loops of each cell. Using such large dimensions would severely lower the device packing density of the IC, thereby increasing manufacturing costs. In addition, because the PROM array of FIG. 3 is created in the interior, active region of the IC device, it is significantly more difficult, if not impossible, to raise the supply voltage V.sub.DD at a specific cell location in order to generate the current required to blow the fuse in that cell without adversely affecting circuitry elsewhere in the IC device.
What is desired is a method for blowing a fuse by using a structure which occupies only a small area in an IC device and can be blown by applying conventional voltage levels to the IC device. A designer would be able to place such a structure nearly anywhere in the IC device, including the active, internal region of the device.